系统开发
虽然使用 shell 和多个 IP 块对 FPGA 设计人员而言并非新概念,这种方法一般需要开发和仿真大量 RTL,多次整合数百
乃至数千独立信号以完成下列连接:
? shell 到验证 IP
? shell 到核设计 IP
? shell 到衍生核设计 IP
鉴于在传统 RTL 设计进程中使用这种方法会因设计和验证工作产生大量额外的工时 (而且如果是在文本编辑器中进
行,还容易发生错误),设计团队一般选择设计和集成所有内容。
Vivado IP 集成器能让这种方法成为可行,*传统的 RTL 文件手工编辑即可迅速完成 IP 集成工作。
使用这一方法具有下列关键特性:
? Vivado IP 目录
? IP 集成器与标准接口
描述
This answer record discusses a known issue with the ChipScope Inserter tool in the 13.2 software, which fails when targeting a Virtex-7 device.
The ChipScope Inserter tool displays an error message similar to the one below:
Inserter fails with ICON core generation error
<CoreGen>:WARNING:encore:175 -
Project options (family='virtex7', device='xc7v485t')
解决方案
If you are using v13.2 of the ChipScope Inserter tool, and targeting a Virtex-7 part, the tool will error and fail.
This is a known issue in the 13.2 software and will be resolved in 13.3. A patch is attached to this Answer Record.
The "readme" file that is included with the patch contains all the necessary information that you need to patch the inserter tool software.